Design-Reuse

Frequency divider IP Listing

1. Programmable Divider ; 2. 5 to 10 Bit dividing facility. ; 3. Poly Phase output facility. ; 4. Ease of customization and fast deliverable IP as per customers need. ; 5. GDSII for ASIC and ... The ...
EDN

Tracking PLL design through the decades, part 1

PLLs (phase-locked loops) are among the most commontypes of analog/mixed-signal circuits on today’sSOC (system-on-chip) ICs. PLLs are essential companionsto the digital-logic circuits and processorson ...
EDN

Programmable octal CMOS clock generator IC produces (almost) any frequency, replaces more complex PLL approach

Clock signals for your system: you can never have enough of them, or if you do, they aren't quite the right ones or don’t have the glitch or jitter performance you need. The CMOS Si5350 and Si5351 ...
Electronics Weekly

ISSCC: Imec develops all-digital PLL

Imec, Rohm and Holst Centre showed off an all-digital PLL for IoT radio transceivers at the 2017 ISSCC. Whereas a PLL is traditionally one of the major power consumers in a radio and can take up to 30 ...
Electronic Design

Smaller PLL Synthesizers Become Design-Friendlier

Phase-locked-loop (PLL) frequency synthesizers are signal sources often employed in many types of electronic equipment. They show up as clock sources in high-frequency instruments and as local ...
Design-Reuse

A 66-mW 3.4Gbps Transmitter PHY for HDMI Applications in 2.5V 40-nm CMOS

This paper presents a low-power Synopsys® DesignWare® High Definition Multimedia Interface Transmitter (HDMI TX) PHY in a 2.5V 40-nm CMOS process. It employs a number of features for IP portability ...