If functional verification already consumes most of the IC logical design flow, as some studies suggest, what's going to happen as chip complexity reaches 10 million or 100 million gates? The answer ...

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, ...

SoC design isn't getting any easier. Escalating IC densities, rising design complexity and increasingly intricate software interactions are conspiring to reduce predictability and drive up cycle-time ...

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at Mentor Graphics; , CEO of Agnisys; , CEO of Test and ...

European research project named best proposal for embedded systems by the EU’s Seventh Framework Programme VERONA, Italy -- April 9, 2008-- In January 2008, work commenced on a European research ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, announces the release of ...

Today's EDA companies now face the primary need for a verification flow that enables complete horizontal reuse of verification environments from concept to silicon and beyond. Big changes are ahead ...

The problem with today's existing methodologies is that verification issubservient to design. This principle requires a shift in paradigm,especially in designing complex electronic systems. Why?

MUNICH & TOKYO & SUNNYVALE, Calif.--(BUSINESS WIRE)--OneSpin Solutions, an EDA company that provides innovative formal assertion-based verification solutions, today announced the adoption of its ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...